Search - freq vhdl

[SCM] freq

Description: 频率计，经过编译与仿真，能够在数码管上显示
Platform: | Size: 1024 | Author: LIMENG | Hits:

Description: 实验四频率计实验要求：设计一个有效位为4位的十进制的数字频率计。 -Experiment IV Cymometer experimental requirements: design of an effective place for the 4 decimal digital frequency meter.
Platform: | Size: 136192 | Author: 朱伟成 | Hits:

[VHDL-FPGA-Verilog] freq

Description: 智能频率计 1. 频率测量范围为1Hz~1MHz 2. 当频率在1KHz以下时采用测周方法其它情　　　　况采用测频方法.二者之间自动转换 3. 测量结果显示在数码管上,单位可以是Hz（Ｈ）、　　　KHz（ＡＨ）或MHz（ＢＨ）。４. 测量过程不显示数据，待测量结果结束后，直接显示结果。 -Intelligent frequency meter 1. Frequency measurement range of 1Hz ~ 1MHz 2. When the frequency of 1KHz weeks following measurement methods used in other circumstances the use of frequency measurement methods. Automatically switch between the two 3. Measurement results have shown that in the digital control, the unit can be Hz (H), KHz (AH) or MHz (BH). 4. Measurement process does not display data until after the end of the measurement results, the direct result will be displayed.
Platform: | Size: 238592 | Author: 谭超 | Hits:

[VHDL-FPGA-Verilog] freq

Description: 数字频率计，七位计数，显示六位，带test模块-Digital frequency meter, seven counts, showed that six, with test module
Platform: | Size: 8402944 | Author: 潘斌 | Hits:

[VHDL-FPGA-Verilog] freq

Description: vhdl语言设计频率计，十进制加法器.运用maxplus2运行，-VHDL language design frequency, the decimal adder. maxplus2 application running,
Platform: | Size: 95232 | Author: lucy | Hits:

[VHDL-FPGA-Verilog] FREQ

Description: 硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.
Platform: | Size: 356352 | Author: czm | Hits:

[Software Engineering] VHDLsourcecode

Description: source code for counter, freq devider, traffic light, stepper motor, flipflop
Platform: | Size: 2048 | Author: ibnudahlan | Hits:

[VHDL-FPGA-Verilog] freq

Description: 应用VHDL语言设计低频数字频率计，选择测频法方案，主要是控制电路，由其产生闸门、清零和锁存等信号。-VHDL, design low frequency digital frequency meter, select the frequency method to program, mainly the control circuit, produced by the gate and the latch so clear signal.
Platform: | Size: 439296 | Author: 付晓 | Hits:

[VHDL-FPGA-Verilog] freq

Description: 本程序是基于vhdl语言的8位16进制频率计，待测频率范围是1HZ~100MHZ。-This procedure is based on the vhdl language 8 16 hex frequency, frequency range tested 1HZ ~ 100MHZ.
Platform: | Size: 695296 | Author: 张东林 | Hits:

[VHDL-FPGA-Verilog] 1

Description: 一个VHDL实现的测频计 LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY freq IS PORT( Fsignal : IN std_logic -- Rst : IN std_logic Gate : IN std_logic Ready : OUT std_logic Data_out : OUT std_logic_vector(31 downto 0) overflow : OUT std_logic ) END freq -A VHDL implementation of frequency meter LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY freq IS PORT (Fsignal: IN std_logic - Rst: IN std_logic Gate: IN std_logic Ready: OUT std_logic Data_out: OUT std_logic_vector (31 downto 0) overflow: OUT std_logic) END freq
Platform: | Size: 1024 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] freq

Description: 在Quartus下VHDL编写的一个频率测试模块，自动转换为十进制数字输出到数码管上。-A frequency test modules written in VHDL in Quartus under are automatically converted to the decimal number is output to the digital tube.
Platform: | Size: 286720 | Author: voldemortqq | Hits:

[Software Engineering] freq

Description: vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块-vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module
Platform: | Size: 2048 | Author: zrf | Hits:

[VHDL-FPGA-Verilog] freq

Description: VHDL入门学习，基于FPGA的频率计设计-Getting started learning VHDL, FPGA-based frequency meter design
Platform: | Size: 5120 | Author: 张立 | Hits:

[VHDL-FPGA-Verilog] dianzhen1616

Description: 16*16点阵动态滚动显示VHDL四个字母共有5个模块，4个子模块，top是顶层模块 1.control，产生地址信号，用来读取数据 2.data_store,64组数据，4*16，根据输入地址来输出对应的数据 3.freq，分频模块，由50M主时钟进行分频，得到系统所需的各个频率 4.display,控制点阵模块，将得到的数据进行输出-display VHDL on 16*16 dot matrix
Platform: | Size: 6320128 | Author: maxiaobo | Hits:

[Embeded-SCM Develop] freq

Description: 基于fpga的简易频率计，使用vhdl语言，可直接使用(FPGA based simple frequency meter, the use of VHDL language, can be used directly)
Platform: | Size: 512000 | Author: zzwww | Hits:

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